1. Field of the Invention
The present invention relates generally to a method of forming a gate dielectric layer for a MOS transistor, and more specifically to a method of forming a gate dielectric layer for a MOS transistor that includes a multi-step post nitridation annealing process.
2. Description of the Prior Art
With the development of very large scale integration (VLSI), the low electricity consumption and high integration of metal-oxide-semiconductor (MOS) transistors makes them suitable to be widely applied in semiconductor processes. A MOS transistor comprises a gate on a substrate and two semiconductor regions (a source and drain) in the substrate, located on each side of the gate and having an electrical characteristic opposite to that of the substrate. The main structure of the gate is composed of a gate oxide layer and a gate conductive layer. When a proper bias is added to the gate, the MOS transistor can be regarded as a solid switch to control the connection of current.
The gate oxide layer is sandwiched by the gate conductive layer and the substrate, and isolates the gate conductive layer from the substrate to provide said function. The performance of this formed MOS transistor such as negative bias temperature instability (NBTI), reliability, yields or circuit leakage relies on the properties of the gate oxide layer. Thus, improving the properties of the gate oxide layer will have a direct effect on the performance of the entire transistor.